1. Field of the Invention
This invention relates to a manufacturing method for a semiconductor device having a notch on the side surface of a gate electrode.
2. Description of the Background Art
To improve the performance of semiconductor devices, development of MOS transistors possessing excellent properties is earnestly required. Furthermore, to realize speedy operations of the semiconductor devices, it is necessary to increase the drain current of the MOS transistor and reduce its parasitic capacitance. Especially, an overlap capacitance appearing in a region where a gate electrode and a source/drain region are overlapped via a gate insulating film gives a significant influence to the transistor characteristics. Hence, reducing the overlap capacitance is a target to be attained.
T. Ghani, et al., IEDM Technical Digest, pp.415-418, 1999 (hereinafter, referred to as non-patent document 1), discloses a method of reducing the overlap capacitance. According to the technique disclosed in the non-patent document 1, a notch is provided at the bottom portion of a gate electrode to reduce the region where a gate electrode and a source/drain region are overlapped via a gate insulating film (hereinafter, referred to as “gate overlap amount Lov”), to reduce the overlap capacitance.
According to the technique disclosed in the non-patent document 1, the formation of notch is limited to the bottom portion of the gate electrode. The gate length of the bottom portion of the gate electrode is shorter than the gate length of its upper portion. Accordingly, the overlap capacitance can be reduced. It becomes possible to obtain a short gate length which was not realized by the ordinary processes. Furthermore, even in the case that a notch is formed at the gate electrode, the gate resistance does not increase because the gate length of an upper portion of the gate electrode remains constant.
Another method of forming a notch at the gate electrode of a MOS transistor is for example disclosed in the Japanese Patent Application Laid-open No. 2002-222947 (hereinafter, referred to as patent document 1) or in the Japanese Patent Application Laid-open No. 9-82958(1997) (hereinafter, referred to as patent document 2). The notch forming method disclosed in the patent document 1 or 2 is based on the characteristics that an oxidizing speed on the sidewall of the gate electrode varies depending on the concentration of impurities contained in the gate electrode. Furthermore, Japanese Patent Application Laid-open No. 2002-305287 discloses a different type of notch forming method.
Although the above-described method of providing a notch on the side surface of the gate electrode is effective in reducing the overlap capacitance, it is also possible to use another method of, for example, providing double sidewalls on the side surface of the gate electrode to reduce the gate overlap amount Lov as disclosed in T. Matumoto, et. al., IEDM Technical Digest, pp.219-222, 2001 (hereinafter, referred to as non-patent document 2) or in K. Ohta, et. al., Extended Abstracts of the 2001 International Conference on SSDM, pp.148-149, 2001 (hereinafter, referred to as non-patent document 3).
As described above, according to the patent documents 1 and 2, the notch is formed by oxidizing the sidewall of the gate electrode and hence the following problem will be caused.
In general, accurately controlling the oxidized amount of the gate electrode is so difficult that, in many cases, the sidewall of the gate electrode is excessively oxidized beyond a portion where the oxidization should be stopped. Thus, it is difficult to obtain desired notch configuration.
In ordinary cases, reducing the gate overlap amount Lov to reduce the overlap capacitance leads to increase in the parasitic resistance of the source/drain region and reduction in the drain current. Accordingly, reduction in the overlap capacitance and increase in the drain current are generally in a tradeoff relationship. Hence, optimizing the performance of the transistor can be realized by designing the gate overlap amount Lov to an appropriate value and accurately implementing it.
However, as described above, according to the techniques disclosed in the above-described patent documents 1 and 2, it is difficult to obtain desired notch configuration. Accurately realizing the gate overlap amount Lov is difficult. Therefore, the techniques disclosed in the above-described patent documents 1 and 2 cannot optimize the performance of the transistor.